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Electronics Design Automation (EDA): Modelling of MEMS Sensors

Motivation

Integrated circuits (microchips), are designed, modeled and simulated in more than 20 discrete design steps. Near the final steps where the design evolves to a physical layout, it is important that the models of the chip used in simulations are realistic, accounting for the electromagnetic behavior of the actual materials and geometries, so as to avoid performance shortcomings due to unforeseen, so called “parasitic”, electrical and electromagnetic properties of the various chip components.

Our EDA CloudFlow Application Experiment aimed to derive such realistic electrical models of certain parts of a MEMS sensor, aiming add to it components and functionality without increasing the overall chip area. The particular MEMS sensors are designed and manufactured by EUROPEAN SENSOR SYSTEMS (ESS).

Goals of the experiment

  • Product innovation:
    • use cloud version of Helic’s modeling software to derive realistic chip models and free-up space on the chip
    • use the freed space to add new on-chip components and thus broaden the market opportunities for the chip
  • Enable the particular innovation by using an on-cloud version of Helic’s software
  • Reduce chip de-risking time by 1.5 weeks for the particular 12 week exercise (10 percent time saving)

Technical impact

In this particular experiment Helic’s cloudified RaptorX parasitics extraction software, helped ESS modify its MEMS chip design and add interfaces for a broader range of devices, while maintaining the same chip dimensions and cost. In particular ESS:

  • freed 5 percent off the chip area, by placing closer together certain on-chip transmission lines, whilst maintaining achieved levels of performance
  • utilized the freed area to add components and extend the ASIC’s ability to interface with all combinations of capacitive sensor structures
  • ensure that is no crosstalk on the chip, without manually implementing pre-modeled generic foundry components

Further than the particular experiment and for more complex designs, IC designers have the following key benefits:

  • Capture hard-to-discover crosstalk between blocks of different hierarchies
  • Include all electromagnetic and substrate effects in the derived models
  • Account for High-frequency resistance, self-inductance, mutual inductance, capacitance and substrate models in a single extracted file
  • Quantify crosstalk between nets across multiple blocks
  • Work on large circuits within realistic time scales

Economic impact

End-User: Savings aspect

From the IC designer perspective, access to Helic’s software over and HPC/cloud – enabled platform, provides a unique pay-per-user flexibility. Helic’s software accepts generic format input (GDSII file of the physical design) and does not constrain the end user to the use of a specific hardware platform/OS or specific Electrical Design software suite.
The time saving benefit from using Cloud Extraction services depends mainly on the complexity of the circuit that needs to be extracted and the capabilities of the cloud hardware. In the case of large designs, and considering that cloud hardware and optimized computing algorithms result in half the extraction time (conservative assumption) this could yield an overall project duration improvement of around 10 percent.

In the present demonstration, since only a small, but crucial, part of the chip was extracted, the improvement due to the small extraction time is negligible. However, if one takes into account the time saved compared to the time needed to utilize alternative strategies to extraction (substitution of metal lines with pre-modeled METAL RESISTOR CELLS and utilization of conservative rules on physical design), then the overall project’s duration benefit is around 10 percent. In terms of production costs reduction, were ESS to directly reduce chip area by 5 percent without adding the extra components, they would achieve a cost saving of approximately 5 percent on wafer costs. For an indicative cost of 0.8 dollars/chip, savings would be in the order of 40,000 dollars (36,700 euros) for 1 million pieces. It must be stressed however, that in this particular instance ESS benefits not from dollar savings on Si area, but on added functionality!

In terms of software license fees savings, should ESS decide to introduce the SaaS version of RaptorX in its design flow and employ it on crucial chip’s blocks, the cost reduction for ESS’s use of the cloud’s extraction scheme vs the standard extraction scheme is in the order of whopping 80-90 percent. This would result in savings compared to the overall EDA tools licensing cost that ESS utilizes, of 25-30 percent, which may be up to 40,000 euros per year.

Additional financial benefits for designers include (a) savings on expensive tape-outs (chip prototypes) and subsequent measurements which show chip misbehavior due to unaccounted parasitics in the model (b) avoiding losses incurred by getting into the market with underperforming and thus underpriced chips, in order to meet customer timescales. Such savings vary widely, depending on chip technology, volume and application area.

CFD Design
End-User: Market prospects

ESS products address a large market of micro-component solutions providers (for smart phones, tablets, ultra-books, and wearable devices). Currently estimated market size is at 3.7 billion dollars whereas with current growth rates this market will have grown to 4.5 billion dollars with ESS’s potential share being at 0.2 percent generating revenues of a ballpark 10 million dollars. The Humidity sensors market alone, which is addressed by the improvements achieved in this experiment, is a fast growing segment, and was estimated at approximately 300 million dollars for 2017, while a single customer alone can bring in a 2.5 million – 3 billion dollars deal if their specification is met.

ISV: New market prospects

Helic, has developed from scratch and has successfully demonstrated a platform-agnostic web version of its RaptorX software, suitable for IP and Design Services SMEs as well as for the Academia. Security concerns over valuable IP leaking to the outside world, are not founded in the case of only partial chip processing, as long as any disclosing elements of the chip design, functionality, end application or customer do not leave the designer premises. Further security enhancements will depend upon the Cloud service provider and any additional security platform employed. Successful market take-up of the SaaS offering, could see Helic gaining revenues from the SME market where Helic’s standard products version are normally outside most SMEs’ budget limits.

The global SME IC designers’ market targeted by Helic is estimated at 20-28 million dollars and Helic could be looking at a 2 percent penetration in 3 years from now. With Helic’s currently envisaged pricing model this sort of penetration could bring another 0.5 million dollars in 3 years from now.

In terms of new jobs, we estimate that 2 new job posts will be created to launch the SaaS product and until a 150,000 euros mark of additional revenue is achieved. Following that, it is estimated that another 1 job post will be created per 100,000 euros of revenue. More job posts may be created due to promotion effects (e.g. via academic usage).

Environmental impact

Amongst other things, Helic’s software can be used to reduce a chip dimension, by allowing chip designers to bring closer together various on-chip components. The two main motivators behind reducing chip size are (a) smaller chips for smaller devices and (b) cost. The former has been an ongoing trend and market requirement from the very beginning of the electronics sector. Cost savings due to chip area reduction is a major driver, since (a) the cost of a printed Si wafer is the same regardless of how many chips have been printed on it and (b) yield improves a lot as chip area is reduced, because the same number of on-wafer defects produce less defective chips.

Raw material savings (Silicon, Si) are minuscule whilst also Si is abundant on the planet.

However, there is a lot to be saved in terms of energy and water by reducing chip size.

Although it is extremely difficult and complex to accurately estimate such savings, we indicatively base our calculations on a 2002 estimation which stipulated that a 2 g (memory) chip requires:

  • 1.6 kg of fossil fuel
  • 72 g of chemicals
  • 32 kg of water

Adapting this gross approximation to our experiment and ESS’s electronics (which, however are not memory chips), we have:

5 percent savings on a relatively small quantity of 1 million of ESS chips originally sized at 1640x1600 um each give approximately of savings in Si chips. Very roughly and not accounting for shrinkage effects in chip packaging, processes, yield and a large number of other parameters, we could obtain savings of:

  • 188 kg of fossil fuel
  • 8.46 kg of chemicals
  • 3.76 tons of water

If the above calculation gets the order of magnitude approximately right, and given that we live in a world with dozens of billions of microchips being produced every year, there is certainly potential for massive savings on natural resources by reducing the size of those chips.